1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having macrocells composed of CMOS transistors.
2. Description of the Prior Art
In a semiconductor integrated circuit device such as an LSI (large-scale integrated circuit), it is customary to apply a voltage to a semiconductor substrate, N well, or the like (i.e. the back gate) and adjust this voltage to compensate for variations in the threshold voltage among transistors, or to maintain the threshold voltage stably at a low level.
More specifically, in the production process of an LSI, it is in some cases inevitable that the transistors near the center of the LSI wafer and those near the periphery of the wafer have different threshold voltages, and such variations in the threshold voltage among transistors are compensated for by adjusting the voltage applied to the back gate. On the other hand, whereas reducing the power-source voltage to reduce power consumption usually leads to a slower operation speed, doing so results in a higher operation speed as long as the voltage applied to the back gate or N well is adjusted in such a way that the threshold voltage exhibits no variations and is kept at a low level.
In a conventional semiconductor integrated circuit device, two separate bias lines are laid so as to extend laterally within a macrocell: one is for the back gate, and the other is for the N well. In addition, a power-source line that is connected to the sources of P-channel MOS transistors and a ground line that is connected to the sources of the N-channel MOS transistors are also laid so as to extend laterally. These four lines are laid in a single wiring layer (specifically, in a first wiring layer).
Laying two extra bias lines in addition to the essential power-source and ground lines for each column (site) in this way means, for example in a case where there are 100 columns, adding 200 extra lines, and, in a case where there are 200 columns, adding 400 extra lines, that is, adding a huge number of extra lines. As a result, inconveniently, much of the wiring area secured for signal lines is occupied by the bias lines.